/*
 *************************************************************************
 * @flie:
 * @author: andy.chen
 * @email:qianxin.chen@qq.com
 * @data: 2019.4.13
 *************************************************************************
 */

#ifndef __2440_H
#define __2440_H

#define     REG(x)					(*(volatile unsigned int *)(x)) 
#define     REG_BYTE(x)				(*(volatile unsigned char *)(x)) 

#define LED1_ON 	rGPFDAT &= ~(1<<4);
#define LED2_ON 	rGPFDAT &= ~(1<<5);
#define LED4_ON 	rGPFDAT &= ~(1<<6);
#define LED1_OFF  	rGPFDAT |= (1<<4);
#define LED2_OFF  	rGPFDAT |= (1<<5);
#define LED4_OFF  	rGPFDAT |= (1<<6);

/* GPIO ------------------------------------------------------------------*/
#define GPACON    REG(0x56000000)	//Port A control
#define GPADAT    REG(0x56000004)	//Port A data

#define GPBCON    REG(0x56000010)	//Port B control
#define GPBDAT    REG(0x56000014)	//Port B data
#define GPBUP     REG(0x56000018)	//Pull-up control B

#define GPCCON    REG(0x56000020)	//Port C control
#define GPCDAT    REG(0x56000024)	//Port C data
#define GPCUP     REG(0x56000028)	//Pull-up control C

#define GPDCON    REG(0x56000030)	//Port D control
#define GPDDAT    REG(0x56000034)	//Port D data
#define GPDUP     REG(0x56000038)	//Pull-up control D

#define GPECON    REG(0x56000040)	//Port E control
#define GPEDAT    REG(0x56000044)	//Port E data
#define GPEUP     REG(0x56000048)	//Pull-up control E

#define GPFCON    REG(0x56000050)	//Port F control
#define GPFDAT    REG(0x56000054)	//Port F data
#define GPFUP     REG(0x56000058)	//Pull-up control F

#define GPGCON    REG(0x56000060)	//Port G control
#define GPGDAT    REG(0x56000064)	//Port G data
#define GPGUP     REG(0x56000068)	//Pull-up control G

#define GPHCON    REG(0x56000070)	//Port H control
#define GPHDAT    REG(0x56000074)	//Port H data
#define GPHUP     REG(0x56000078)	//Pull-up control H

#define GPJCON    REG(0x560000d0)	//Port J control
#define GPJDAT    REG(0x560000d4)	//Port J data
#define GPJUP     REG(0x560000d8)	//Pull-up control J

#define MISCCR    REG(0x56000080)	//Miscellaneous control
#define DCLKCON   REG(0x56000084)	//DCLK0/1 control
#define EXTINT0   REG(0x56000088)	//External interrupt control register 0
#define EXTINT1   REG(0x5600008c)	//External interrupt control register 1
#define EXTINT2   REG(0x56000090)	//External interrupt control register 2
#define EINTFLT0  REG(0x56000094)	//Reserved
#define EINTFLT1  REG(0x56000098)	//Reserved
#define EINTFLT2  REG(0x5600009c)	//External interrupt filter control register 2
#define EINTFLT3  REG(0x560000a0)	//External interrupt filter control register 3
#define EINTMASK  REG(0x560000a4)	//External interrupt mask
#define EINTPEND  REG(0x560000a8)	//External interrupt pending
#define GSTATUS0  REG(0x560000ac)	//External pin status
#define GSTATUS1  REG(0x560000b0)	//Chip ID(0x32440000)
#define GSTATUS2  REG(0x560000b4)	//Reset type
#define GSTATUS3  REG(0x560000b8)	//Saved data0(32-bit) before entering POWER_OFF mode 
#define GSTATUS4  REG(0x560000bc)	//Saved data0(32-bit) before entering POWER_OFF mode 

/* Memory Controller Definitions */
#define     BWSCON                   REG(0x48000000)	//Bus Width and Wait Status Ctrl
#define     BANKCON0                 REG(0x48000004)	//Bank 0 Control Register       
#define     BANKCON1                 REG(0x48000008)	//Bank 1 Control Register       
#define     BANKCON2                 REG(0x4800000C)	//Bank 2 Control Register       
#define     BANKCON3                 REG(0x48000010)	//Bank 3 Control Register       
#define     BANKCON4                 REG(0x48000014)	//Bank 4 Control Register       
#define     BANKCON5                 REG(0x48000018)	//Bank 5 Control Register       
#define     BANKCON6                 REG(0x4800001C)	//Bank 6 Control Register       
#define     BANKCON7                 REG(0x48000020)	//Bank 7 Control Register       
#define     REFRESH                  REG(0x48000024)	//SDRAM Refresh Control Register
#define     BANKSIZE                 REG(0x48000028)	//Flexible Bank Size Register   
#define     MRSRB6                   REG(0x4800002C)	//Bank 6 Mode Register          
#define     MRSRB7                   REG(0x48000030)	//Bank 7 Mode Register          

#endif
